 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ATLV Features * * * * * * * Specifically Designed for Battery Powered Applications 1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts Static Current Drain of <75 nA at 1.0 Volts 200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts 1.0 Drawn Gate Length CMOS Gate Arrays All Package Styles Offered Including TQFP and TAB Improved Product Testability Using Serial Scan, Boundary Scan, and JTAG Second Source Existing ASIC Design in Atmel's ATLV via Design Translation. Improved Performance and Lower Cost Description The ATLV Series CMOS gate arrays employ 1.0 -drawn, double-level metal, Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced manufacturing facility. The arrays utilize an enhanced channelless architecture which results in greater than 50 percent usable gates. Atmel's flexible design system uses industry design standards and is compatible with popular CAD/CAE software and hardware packages. The customer can start designing with the ATLV series today using existing CAD/CAE tools. ATLV Series Ultra Low Voltage Gate Arrays ATLV2 ATLV3 ATLV5 ATLV7 ATLV10 ATLV15 ATLV20 ATLV35 ATLV Array Organization Device Number ATLV2 ATLV3 ATLV5 ATLV7 ATLV10 ATLV15 ATLV20 ATLV35 Raw Gates 2,000 3,000 5,000 7,000 10,000 15,000 22,000 35,000 Routable Gates 1,400 1,600 2,800 4,400 6,600 8,000 12,000 18,000 Max Pin Count 44 68 84 100 120 144 160 208 Max I/O(1) Pins 36 60 76 92 112 136 152 192 Gate(2) Speed 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns 1.3 ns Notes: 1. Absolute maximum I/O pins is maximum pin count minus 8. Additional power and ground pins are assumed to be required to support simultaneous switching outputs as pin count increases. 2. Nominal 2 input nand gate with a fan out of 2 at 1.5 volts, room temperature. 0261B 1 ATLV Design Design Systems Supported Atmel supports the major CAE/CAD software systems with complete macro cell libraries (symbols, timing and function), as well as utilities for checking the netlist and accurate pre-route delay simulations. Atmel uses Cadence's Verilog-XL as our golden simulator. Design systems which are supported include Cadence, Viewlogic, Mentor, and Synopsys. Design Options Schematic Capture Schematic capture and simulation are performed by the customer using an Atmel supplied macro cell library. The customer can also receive complete back annotation delay data for post-route simulation. VHDL/Verilog-HDL Atmel can accept Register Transfer level (RTL) designs for VHDL (MIL-STD-454, IEEE STD 1076) or Verilog-HDL format. Atmel fully supports Synopsys for VHDL simulation as well as synthesis. Design via VHDL or VerilogHDL is the preferred method of performing a gate array design. Design Flow While Atmel provides four options for implementing a gate array design, they all have the same basic flow. Data base acceptance is the first milestone. This is when Atmel receives and accepts the complete design data base. Preliminary design review is where the performance of the design is set based on the Cadence simulation. Final design review is the last review of the design before making masks. The back annotation data is incorporated into the simulations. After final design review masks are released and prototypes in ceramic packages are delivered. ASIC Design Translation Atmel has successfully translated dozens of existing designs from most major ASIC vendors (LSI Logic, Oki, NEC, Fujitsu and others) into our gate arrays. These designs have been optimized for speed, gate count, modified to add logic or memory, or replicated for a pin-for-pin compatible, drop-in replacement. ATLV Gate Array Design Flow Customer Atmel Cell Library Gate Array Design Translation Design Synthesis FPGA/EPLD Conversions -VHDL -Verilog-HDL Atmel Data Base Acceptance Atmel Simulation and Verification Atmel Customer Preliminary Design Review Atmel Physical Design, Simulation and Verification Atmel Customer Final Design Review Atmel Customer Prototype Delivery Atmel 2 ATLV ATLV FPGA and EPLD Conversions Atmel has successfully translated existing FPGA/EPLD designs from most major vendors (Xilinx, Actel, Altera, AMD & Atmel) into our gate arrays. The design can be optimized for speed or power consumption, modified to add logic or memory or replicated for a pin-for-pin compatible, drop-in replacement. Atmel frequently combines several devices onto a single gate array. at the transistor level and verified through measurements made on fabricated test arrays. The symbols for the ATLV cell library are compatible with Atmel's ATL (1.0 3.3 and 5.0 V) and ATL80 (0.8 3.3 and 5.0 V) cell libraries. Existing designs can be easily migrated to the ATLV series. Characterization has been performed over commercial temperature and 1.0 to 3.0 volts, to ensure that the simulation accurately predicts the performance of the finished product. Atmel is continually expanding the ATLV series cell library with both soft and hard macros. Check with your sales representative for the most recent additions. ATLV Series Cell Library Atmel's ATLV series gate arrays use cells from an accurately modeled and highly flexible library. The cell library contains over 120 hard-wired data path elements and has been characterized via extensive SPICE modeling Cell Guide Buffers and Inverters 1x Buffer 2x Buffer 2x Buffer with Enable 2x Buffer with Enable Low 3x Buffer 4x Buffer 8x Buffer 12x Buffer 16x Buffer Delay Buffer 2.0 ns Delay Buffer 3.5 ns Delay Buffer 8.0 ns AND, NAND, OR, NOR Gates 2 input AND 3 input AND 4 input AND 5 input AND 2 input NAND Dual 2-input NAND 3 input NAND 4 input NAND 5 input NAND 6 input NAND 8 input NAND Multiplexers 2:1 MUX Inverting 2:1 MUX w/o Buffered Inputs Inverting 2:1 MUX w/o Buffered Inputs 2:1 MUX with Enable Low Quad 2:1 MUX with Enable Quad 2:1 MUX Inverting 3:1 MUX w/o Buffered Inputs Inverting 3:1 MUX w/o Buffered Inputs 4:1 MUX 4:1 MUX w/o Buffered Inputs 4:1 MUX w/o Buffered Inputs 8:1 MUX 8:1 MUX with Enable Low 2 input NOR Dual 2 input NOR 3 input NOR 4 input NOR 5 input NOR 8 input NOR 2 input OR 3 input OR 4 input OR 1x Inverter Dual 1x Inverter Quad 1x Inverter Quad Tri-state Inverter 2x Inverter Dual 2x Inverter 2x Tri-state Inverter 3x Inverter 4x Inverter 8x Inverter 10x Inverter 3 Cell Guide AND/OR, OR/AND Gates 3 input AND OR INVERT 4 input AND OR INVERT 6 input AND OR INVERT Exclusive OR/NOR Gates 1 bit Adder 1 bit Adder with Buffered Outputs 7 input Carry Lookahead Decoders 2:4 Decoder 2:4 Decoder with Low Enable Flip-flops/Latches D Flip-flop D Flip-flop with Clear/Preset D Flip-flop with Clear D Flip-flop with Reset D Flip-flop with Set D Flip-flop with Set/Reset JK Flip-flop JK Flip-flop with Clear/Preset JK Flip-flop with Clear Scan Cells Set-scan Register Set-scan Register with Clear and Preset Set-scan Register with Reset I/O Options Input, Output, Bidirectional, Tristate Output, Internal Clock Driver and Oscillator Output Drive Value Programmable from 0.5 mA to 6 mA in 0.5 mA increments with Slew Rate Control CMOS Operation Testable NAND Gate on Input (Bidirectional, Input) Inverting and Non-inverting Input Buffers (Bidirectional, Input) Pullup Resistor - 10K to 310K Pulldown Resistor - 3.5K to 108.5K Set-scan Register with Set Set-scan Register with Set and Reset LATCH LATCH with Complementary Outputs LATCH with Inverted Gate Signal QUAD LATBG with Common Gate Signal QUAD Inverting LATCH LATCH with Reset LATCH with Set LATCH with Set and Reset 3:8 Decoder with Low Enable 2 input Exclusive OR 2 input Exclusive NOR 3 input OR AND INVERT 4 input OR AND INVERT 8 input OR AND INVERT 4 ATLV ATLV CMOS Input Interface Characteristics Interface CMOS Logic High 0.90 VDD Logic Low 0.1 VDD Switchpoint VDD /2 Typical Absolute Maximum Ratings* Operating Temperature .......................-40C to +85C Storage Temperature ........................-65C to +150C Voltage on Any Pin with Respect to Ground ....................-2.0 V to +5.5 V1 Maximum Operating Voltage ...............................5.5 V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: 1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is VDD + 0.75V dc which may overshoot to +7.0 V for pulses of less than 20 ns. 1.5 Volt DC Characteristics Applicable over recommended operating range from Ta = -40C to +85C, VDD = 1.0 V to 3.0 V (unless otherwise noted) Symbol IIH IIL Parameter Input Leakage High Input Leakage Low (no pull-up) Output Leakage (no pull-up) Output Short Circuit Current (3 x Buffer)(2) CMOS Input Low Voltage CMOS Input High Voltage CMOS Switching Threshold Output Low Voltage Output buffer has 12 stages of drive capability with 0.5 mA IOL per stage. Output High Voltage Output buffer has 12 stages of drive capability with -0.5 mA IOH per stage. Static Current Input Leakage Low (no pull-up) VDD=1.5 V, 25C IOL=as rated VDD=1.5 V 0.8 x VDD 0.75 0.2 x VDD Test Condition VIN=VDD, VDD=1.8 V VIN=VSS, VDD=1.8 V -10 Min Typ 1 x 10-5 -1 x 10-5 Max 10 Units A A A mA mA V V V V IOZ IOS VIL VIH VT VOL VIN=VDD or VSS, VDD=3.6 V VDD=1.8 V, VOUT=VDD VDD=1.8 V, VOUT=VSS -10 5 -60 1 x 10-5 25 -25 10 60 -5 0.2 x VDD VOH IOH=as rated VDD=1.5 V 0.8 x VDD V IDD 1.0 V 3.0 V < 75 < 1.0 nA A Note: 2. This is the specification for the 3 x Output Buffer. Output short circuit current for other outputs will scale accordingly. Not more than one output shorted at a time, for a maximum of one second, is allowed. 5 AC Characteristics Delay vs VDD 2 Delay vs Fanout 4 3.5 Prop Delay (ns) Prop Delay (ns) 1.5 3 2.5 2 1.5 1 0.5 1 0.5 0 1.2 1.5 2.0 Volts NAND2 - 2 input NAND Temp = 25C FO = 2 0 2.5 3.0 2 4 6 Fanout 8 16 1.5 Volts VDD NAND2 - 2 input NAND Temp = 25C Delay vs Temperature 2 Current Drain vs Voltage 0.9 0.8 Prop Delay (ps) 1.5 IDD (nA) 0.7 0.6 0.5 0.4 0.3 1 0.5 0.2 0.1 0 -30 0 25 50 0 0.5 1.0 1.5 2.0 2.5 3.0 Temperature (C) 1.5 Volts VDD VDD (Volts) Temp = 25C NAND2 - 2 input NAND FO = 2 6 ATLV ATLV I/O Buffer DC Characteristics Symbol CIN COUT CI/O Parameter Capacitance Input Buffer (Die) Capacitance Output Buffer (Die) Capacitance Bi-Directional Test Condition 1.5 V 1.5 V 1.5 V Min Typ 2.4 5.6 6.6 Max Units pF pF pF I/O Buffers * * Programmable output drive 0.5 to 6 mA I OL, -4.5 to -6 mA IOH for 1.5 V) 3000 volts ESD protection The ATLV series input/output ring contains the I/O buffer circuitry capable of sourcing and sinking currents up to 6 mA, and responds to CMOS logic levels. I/O locations on this ring can accommodate bidirectional cells. By following a set of design rules, Test Compiler can automatically insert the scan cells and generate test vectors providing greater than 95% fault coverage. This is the easiest and least expensive method for designing testability into a gate array design. Advanced Packaging Atmel supports a wide variety of standard packages for the ATLV series, but also offers its ATLV series gate arrays in packages that are custom designed to maintain the performance obtained in the silicon. All of Atmel's standard packages have been characterized for thermal and electrical performance. When a standard package can't meet a customer's needs, Atmel's package design center can develop a package to precisely fit the application. The company has delivered custom-designed packages in a wide variety of configurations, including Tape Automated Bonding (TAB) packages. Atmel's domestic packaging facility manufactures commercial, industrial and Class B. Design for Testability Atmel supports a full range of Design-for-Test improvement techniques which reduce design and prototype debug time, production test time, and board & system test time. These techniques can also improve system level test and diagnostic capability. The ATLV arrays support the Joint Test Action Group (JTAG) boundary scan architecture. The required soft and hard macros to implement IEEE 1149.1 compliant architecture are available in our macro cell library. Use of JTAG allows for scan testing with only 4-5 additional pins required. Atmel can also provide automatic high fault coverage test pattern generation (ATPG) via Synopsys Test Compiler. Packaging Options Package Type PQFP TQFP PLCC CPGA CQFP BGA Pin Count 44, 52, 64, 80, 100, 120, 128, 132, 144, 160, 184, 208, 240, 304 44, 48, 52, 64, 80, 100, 120, 128, 144, 160, 176, 216 20, 28, 32, 44, 52, 68, 84 64, 68, 84, 100, 124, 144, 155, 180, 223, 224, 299, 391 64, 68, 84, 100, 120, 132, 144, 160, 224, 340 121, 169, 225 Cadence, Mentor, Synopsys, Verilog-XL, Viewlogic, and Xilinx may be registered trademarks of others. 7 |
Price & Availability of ATLV15
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |